Method for fabricating an integrated pin diode and associated circuit arrangement

ABSTRACT

A method for producing an integrated PIN photodiode. The PIN photodiode contains a doped region of a first conduction type near the substrate and a doped region that is remote from the substrate. The doped region that is remote from the substrate has a different construction type than the region near the substrate. In addition, an intermediate region provided that is a range between the doped region remote from the substrate and the doped region near the substrate. The intermediate region is undoped or provided with weak doping.

This application is the national stage application of internationalapplication number PCT/DE03/02740, filed on Aug. 14, 2003, which claimsthe benefit of priority to German Patent Application 102 41156.5, filedon Sep. 5, 2002, incorporated herein by reference.

The invention relates to a method in which a pin diode carried by acarrier substrate is produced. The pin diode contains a doped region ofa first conduction type, which, in respect of the carrier substrate, isnear the substrate, a doped region which, in respect of the substrate,is remote from the substrate and is of a different conduction type thanthe region near the substrate, and an intermediate region, which isarranged between the region remote from the substrate and the regionnear the substrate and is undoped or provided with a weak doping incomparison with the doping of the region near the substrate and thedoping of the region remote from the substrate. Further regions can bearranged between the intermediate region and the region near thesubstrate, and between the intermediate region and the region remotefrom the substrate, in order to improve the electrical properties of thepin diode.

A pin diode is a diode having a layer sequence p, i and n, where pdenotes a highly p-doped region, i denotes an intrinsically conductingor intrinsic or else only weakly n- or p-doped region, and n denotes ahighly n-doped region. The pin junction differs from a pn junctionprimarily by virtue of the intrinsic or the weakly doped intermediateregion. Owing to their electrical properties, pin diodes are used asrectifier diodes for reverse voltages of more than 100 volts. Fastswitching diodes in the microwave range constitute a further area ofapplication. Since the reverse current of the pin diode principallydepends on the charge generation in the i zone, this diode is alsoemployed as a radiation detector, e.g. in nuclear technology, or as apin photodiode, in particular for detecting light in the wavelengthrange between approximately 400 nanometers to about one micrometer. Inparticular, pin diodes have a high sensitivity and high detectionspeeds.

Integrated pin diodes have a greater detection sensitivity and a higherfrequency bandwidth than individual semiconductor components since theyare monolithically connected directly to integrated circuits.

It is an object of the invention to specify a simple method forfabricating an integrated pin diode. Moreover, the intention is tospecify an associated integrated circuit arrangement.

The invention is based on the consideration that the integrated pindiode should be fabricated by a method which can easily be embedded inthe overall process for fabricating an integrated circuit arrangementand which also as far as possible contains method steps which can alsobe utilized for producing other electrically active structures in theintegrated circuit arrangement.

In the method according to the invention, at least one electricallyconductive terminal region which leads to the region near the substrateis produced. The terminal region is arranged in a layer containing theintermediate region and penetrates through this layer, in onerefinement, from said layer's interface remote from the substrate as faras said layer's interface near the substrate. In the case of such amethod, the region near the substrate is a so-called “buried” region,also referred to as buried layer, in respect of the layer containing theintermediate region. In contrast to a so-called mesa layer stack, themethod for fabricating a buried region is simpler. Moreover, in themethod according to the invention, the pin diode is not connected viathe substrate, but rather via at least one separate terminal region.This results in degrees of freedom for the integration of the pin diodeinto the integrated circuit arrangement. Moreover, it becomes possiblefor other structures of the integrated circuit arrangement, for exampleshielding wells for specific parts of the integrated circuitarrangement, also to be fabricated at the same time as the pin diode.This possibility will be explained in more detail further below.

In one development of the method according to the invention, a dopeddecoupling region is produced at the same time as the region near thesubstrate. A circuit arrangement carried by the carrier substrate isproduced in such a way that the decoupling region extends between oneportion of the components and the carrier substrate. By contrast, nodecoupling region lies between the other portion of the components andthe carrier substrate. This measure makes it possible, withoutadditional process engineering outlay, to produce a decoupling regionwhich, by way of example, shields circuit portions of the integratedcircuit arrangement which cause interference from other circuitportions. On the other hand, however, particularly sensitive circuitportions can also be shielded from the rest of the circuit. In the firstcase, parasitic currents cannot be impressed e.g. by capacitive couplinginto the substrate. In the second case, parasitic currents or voltagesdo not pass e.g. by means of capacitive coupling from the substrate tothe sensitive circuit portions. A combination of both measures leads toimproved shielding. Strongly interfering circuit portions are e.g.digital circuits or output amplifiers. Particularly sensitive circuitportions are e.g. preamplifiers.

In a next development of the method for fabricating a pin diode, aterminal region leading to the decoupling region is produced at the sametime as the terminal region leading to that layer of the pin diode whichis near the substrate. This means that no additional process steps arerequired for the fabrication of the decoupling region terminal region.The decoupling region can be put at a predetermined potential via thedecoupling region terminal region. Moreover, the decoupling regionterminal region can be used to produce so-called extraction diodes whichextract interference voltages and interference currents from theintegrated circuit arrangement. This possibility will be explained inmore detail further below.

In a next development, the decoupling region terminal region and thedecoupling region form a shielding well which surrounds a regionencompassed by the shielding well completely or, relative to the sideareas and the base area of the encompassed region, partially, i.e. by atleast fifty percent or even by at least seventy five percent. Theshielding effect is greater, the more completely the encompassed regionis enclosed. However, interruptions in the shielding are also possiblein order, by way of example, to enable a simple process implementationfor other reasons.

In a next development, in the plane or in the layer in which that regionof the pin diode which is near the substrate and the decoupling regionare situated, regions situated outside said regions are provided with adoping of a different conduction type. This makes it possible toinsulate the region near the substrate and the decoupling region orindividual decoupling regions in the plane or layer from one another ina simple manner. In one refinement, an oxide covering the region nearthe substrate and an oxide covering the decoupling region is utilizedfor masking an implantation. A simplified process implementation resultsin comparison with a lithography method.

In a next development, the terminal region leading to that region of thepin diode which is near the substrate and the decoupling region terminalregion are produced with the fabrication of a deep trench whichpreferably has a depth that is at least twice its width. By way ofexample, the trench has a depth of above ten micrometers, of abovefifteen micrometers or even of above twenty micrometers. The trench hasa width of less than five micrometers, for example. As an alternative,the terminal regions are fabricated with the aid of a diffusion processin which dopants diffuse from a region remote from the substrate as faras the layer near the substrate or as far as the decoupling layer. Givena diffusion length of ten micrometers, for example, the terminal regionshave a width of seven micrometers, for example. In comparison with thearea occupied by the pin diode, however, such a width is an acceptablevalue in respect of the required circuit area. Methods withimplantations of a depth of one or more micrometers are also used tofabricate the terminal regions.

In another development, the layer containing the intermediate region isfabricated by an epitaxy process. In one refinement, base material forat least one embedding region, which serves for embedding components ofthe integrated circuit arrangement, is simultaneously produced duringthe epitaxy process. The embedding region is also referred to as theso-called bulk. An epitaxy process is a simple possibility for producinglayers covering buried layers. However, there are also otherpossibilities, for example a high-energy ion implantation. Dopedsemiconductor regions can also be fabricated in a simple manner by meansof an epitaxy process, for example by in-situ doping during the growthof the epitaxial layer.

In one development with an epitaxy process, the epitaxy process isconducted in at least two stages. The epitaxial growth is interrupted atthe end of the first stage. A different process not connected with anepitaxial growth is then executed. In one refinement, this is a dopingprocess for fabricating a doping which differs from the doping of theepitaxial layer. This measure makes it possible to produce, in a simplemanner, further buried regions in addition to that region of the pindiode which is near the substrate and in addition to the decouplingregion. The growth of the epitaxial layer is then continued after theother process has been carried out. This procedure means that previouslycustomary methods for fabricating the components of the integratedcircuit arrangement can continue to be utilized unchanged.

In a next development, the terminal region leading to that region of thepin diode which is near the substrate encompasses the intermediateregion in the lateral direction completely. This measure makes itpossible to electrically insulate the intermediate region from theremaining constituent parts of the integrated circuit arrangement in asimple manner.

In a next development, the layer containing the intermediate region is asemiconductor layer which preferably has regions with differentconduction types. By way of example, the semiconductor layer is based ona monocrystalline material, e.g. on monocrystalline silicon. However,mixed-crystal semiconductors are also used, such as gallium arsenide.

In a next development, the decoupling region adjoins material with adifferent electrical conductivity type than the decoupling region. Thismeasure results in pn diodes or np diodes which have the function ofextraction diodes and extract interfering charge carriers orinterference currents from the region adjoining the decoupling region orprevent the currents from passing to the region to be shielded onaccount of a blocking effect.

The invention additionally relates to an integrated circuit arrangementhaving a PIN diode, which can be fabricated by the method according tothe invention or by one of its developments. The abovementionedtechnical effects thus also apply to the circuit arrangement and itsdevelopments.

Exemplary embodiments of the invention are explained below withreference to the accompanying drawings, in which:

FIG. 1 shows an integrated circuit arrangement with pin diode andshielding well, and

FIGS. 2A to 2D show fabrication stages in the fabrication of theintegrated circuit arrangement.

FIG. 1 shows an integrated circuit arrangement 10 containing a p-dopedsubstrate 12, a pin photodiode 14, a shielded region 16 or a pluralityof shielded regions and a circuit region 18 or a plurality ofnonshielded circuit regions.

The substrate 12 is part of a semiconductor wafer, for example. A buriedn⁺-type region 20 and a buried n⁺-type region 22 have been produced onthe substrate 12 for example by the method explained below withreference to FIG. 2A, n⁺ denoting a high dopant concentration of dopantswhich lead to an n conduction type, i.e. of arsenic or phosphor forexample. Situated between the regions 20 and 22 are buried p⁺-typeregions 24, 26 and 28 lying in the same plane.

The region 20 belongs to the photodiode 14, which is shown laterallyinterrupted in FIG. 1. By way of example, the photodiode 14 has anextent of fifty micrometers. Situated above the region 20 is anintermediate region 30 of the photodiode 14, which is weakly n-dopedi.e. n⁻. The intermediate region 30 is completely surrounded laterallyby a for example annular terminal region 32, which is n-doped, but witha higher dopant concentration than the intermediate region 30. At itssection 34 remote from the substrate, the terminal region 32 is n⁺-dopedin order to ensure a low contact resistance. Interconnects 36 and 38penetrate through one or more metalization layers 40 of the integratedcircuit arrangement 10 and lead to the section 34 of the terminal region32.

Situated on the intermediate region 30 is a p⁺-doped region 42, whichforms the anode of the photodiode 14. An interconnect 44 penetratesthrough the metalization layers 40 and is connected to the region 42.

Situated above the region 42 is a cutout 46 in the metalization layers40. Light can pass through the cutout 46 to the photodiode 14 in orderto influence the electrical properties thereof. The cutout 46 isconfigured such that incident light can penetrate into the photodiode 14as completely as possible, e.g. through the use of an antireflectionlayer.

Situated in the same plane as the intermediate region 30 are p-dopedregions 48 to 54 of a layer 55, which also contains the intermediateregion 30. The regions 48 and 50 adjoin the terminal region 32 outsidethe photodiode 14. The region 52 forms a so-called bulk or circuitsubstrate and is part of the shielded region 16. Laterally, the region52 is bounded by a terminal region 56, which is likewise annular, forexample, and reaches as far as the decoupling region 22 and separatesthe region 52 from the region 50 and 54.

The terminal region 56 and the region 22 form a shielding well whichproduces functions of a reverse-biased extraction diode. Situated withinthe shielded region 16 are components with strong interference emission,for example an npn transistor 58 and further components 60, e.g. CMOScomponents (complementary metal oxide semiconductor) or else with one ormore passive components, e.g. coils. The npn transistor 58 and thecomponents 60 have been fabricated by standard fabrication methods.

Thus, by way of example, the npn transistor 58 contains a buriedcollector terminal region 62, which is heavily n-doped, i.e. n⁺, andleads to a collector region 64. The collector region 64 is weaklyn-doped, i.e. n⁻. Situated above the collector region 64 is a baseregion 66 which is heavily p-doped, and an emitter region 68, which isheavily n-doped. In the region of the transistor 58, the metalizationlayers 40 are penetrated by interconnects 70, 72 and 74, for example,which lead in this order to the base region 66, to the emitter region 68and to the collector terminal region 62.

The terminal region 56 is likewise n-doped and has a section 76 remotefrom the substrate, said section being n⁺-doped. Interconnects 78 and 80lead to the terminal region 56 and serve for example for applying apositive operating voltage potential UP to the terminal region 56 andthus also to the layer 22, which form the cathode of a reverse-biasedextraction diode. The extraction diode completely shields noise currentswhich might pass into the substrate 12.

The regions 52 and 54 are also referred to as p-well.

The region 18 of the integrated circuit arrangement contains amultiplicity of electronic components 82 which are indicated by threedots in FIG. 1. Interference produced by the transistor 58 and thecomponents 60 cannot penetrate to the components 82 on account of theshielding by the shielding well formed from the terminal region 56 andthe region 22.

FIG. 1 additionally illustrates so-called field oxide regions 84 to 100,which are composed of silicon dioxide, for example, and electricallyinsulate individual components or functional units of components withrespect to one another.

In another exemplary embodiment, the interconnects in the metalizationlayers 40 connect different components of the integrated circuitarrangement 10, e.g. the photodiode 14 to a transistor.

FIG. 2A shows a first fabrication stage during the fabrication of theintegrated circuit arrangement 10. Firstly a silicon dioxide layer 110is produced on the substrate 12, for example by thermal oxidation. Thethickness of the silicon dioxide layer 110 is fifty nanometers, forexample. A silicon nitride layer 112 is then deposited, which, by way ofexample, likewise has a thickness of fifty nanometers.

A lithography method for producing an implantation mask for theimplantation of dopants for the layers 20 and 22 is then carried out. Tothat end, a photoresist layer 114 is applied over the whole area andpatterned in a subsequent exposure and development step in such a way asto produce cutouts 116 and 118 above the regions in which the regions 20and 22 are intended to be produced. Afterward, the silicon nitride layer112 is removed selectively with respect to the silicon dioxide layer 110in the regions not covered by the photoresist 114, for example in a dryetching method. After the patterning of the silicon nitride layer 112,an ion implantation is carried out in order to implant arsenic orantimony ions, for example, see arrows 120.

As shown in FIG. 2B, the residual remainder of the photoresist layer 114is then removed. Afterward, a local oxidation is carried out, thickeroxide regions 130 being produced in the uncovered regions of the silicondioxide layer 110. The dopants in the regions 20 and 22 are alsoactivated during the oxidation.

As shown in FIG. 2C, the residues of the nitride layer 112 are thenremoved, for example with the aid of an etching method. The regions 24to 28 are then produced with the aid of an ion implantation 140. By wayof example, boron is implanted. The energy during the implantation isdimensioned such that the boron ions do not penetrate through the oxideregions 130. By contrast, regions of the silicon dioxide layer 110 whosethickness did not change during the production of the oxidation regions130 are penetrated by the boron ions.

As shown in FIG. 2D, the oxide regions 130 and the residual regions ofthe silicon dioxide layer 110 are subsequently removed. A layer 55 isapplied to the layers 20 and 22 and the regions 24, 26 and 28 by anepitaxy method. The layer 55 is weakly n-doped, for example. In theexemplary embodiment, the layer 55 has a thickness of 10 micrometers.The dopant concentration in the layer 55 is 5-10¹³ particles per cubiccentimeter, by way of example.

A thin silicon dioxide layer 152 is subsequently applied to the layer55. Afterward, in a lithography method, a photoresist layer 154 isapplied and patterned as a mask for a subsequent ion implantation. Inthe photoresist layer 154, cutouts 156 to 162 are the produced at theregions lying above the edges of the regions 20 and 22. An ionimplantation is then carried out, for example using phosphorus ions. Theenergy during the ion implantation is dimensioned such that thephosphorus ions do not penetrate through the photoresist layer 154.Consequently, the phosphorus ions pass only into original doping regions164 to 170 directly below the cutouts 156 to 162. By way of example, thedopant concentration in the original doping regions 164 to 170 is 10¹⁶dopant particles per cubic centimeter. The ion implantation isrepresented by arrows 172 in FIG. 2D.

Residues of the photoresist layer 154 are then removed. Aphototechnology is used to produce a new photoresist mask having cutoutsin regions in which the layer 55 is intended to be p-doped. The regions48, 50, 52 and 54 below the silicon dioxide layer 152 are then dopedwith the aid of an ion implantation, for example using boron ions.

A diffusion process is then carried out, for example using a diffusionfurnace. In this case, firstly the dopants diffuse from the originaldoping regions 164 to 170 as far as the regions 20 and 22, respectively,the terminal regions 32 and 56 being formed. The dopants are alsodistributed within the regions 48, 50, 52 and 54 and lead to a pconduction type in said regions 48, 50, 52 and 54.

In another process variant of the method explained with reference toFIG. 2B, an additional lithography method is performed instead of thelocal oxidation. In this case, it is not necessary to apply a siliconnitride layer 112. The use of a lithography method additionally makes itpossible to achieve a situation in which, by way of example, only theregions 24 and 26 are produced, but not the region 28.

In a next process variant, a phosphorus glass coating is utilizedinstead of the ion implantation in order to produce the doping regions.

In another process variant, the terminal regions 32 and 56 are producednot by diffusion but rather by the production of deep trenches intowhich doped polysilicon or else a metal is then introduced.

1. A method for fabricating an integrated pin diode: producing a dopedregion of one conduction type which is near a carrier substrate;producing a doped region remote from the substrate, which is furtheraway from the carrier substrate than the region near the substrate andis of a different conduction type than the conduction type of the regionnear the substrate; producing an intermediate region, which is arrangedbetween the region near the substrate and the region remote from thesubstrate and is undoped or provided with a weak doping in comparisonwith the doping of the region near the substrate and the doping of theregion remote from the substrate; producing at least one electricallyconductive terminal region, which leads to the region near thesubstrate, in a layer containing the intermediate region; producing adoped decoupling region at the same time as the region near thesubstrate, the decoupling region having the same conduction type as theregion near the substrate; producing a circuit arrangement carried bythe carrier substrate and containing at least two electronic components;and producing a circuit substrate, which is arranged between thedecoupling region and at least one of the components, and the circuitsubstrate forming a pn diode or an np diode with the decoupling region,the decoupling region being arranged between one portion of thecomponents and the carrier substrate and not between the other portionof the components and the carrier substrate, and in a layer in which theregion near the carrier substrate and the decoupling region arearranged, regions outside the region near the substrate and thedecoupling region are provided with a doping of a different conductiontype from the region near the substrate and the decoupling region or areundoped.
 2. The method as claimed in claim 1, wherein the terminalregion penetrates through the layer from an interface remote from thesubstrate as far as an interface near the substrate.
 3. The method asclaimed in claim 1, comprising producing an electrically conductivedecoupling region terminal region at the same time as the production ofthe terminal region leading to the region near the substrate.
 4. Themethod as claimed in claim 3, wherein the decoupling region terminalregion and the decoupling region form a shielding well which completelysurrounds a region encompassed by the shielding well.
 5. The method asclaimed in claim 3, wherein, in the layer in which the region near thesubstrate and the decoupling region are arranged, the regions outsidethe region near the substrate and the decoupling region are providedwith a doping of a different conduction type, an oxide covering theregion near the substrate and the decoupling region serve for maskingimplantation.
 6. The method as claimed in claim 1, wherein at least oneof: the terminal region is produced with fabrication of a trench; theterminal region is fabricated with the aid of a diffusion process inwhich dopants diffuse from a region remote from the substrate as far asthe layer near the substrate; or the terminal region is produced by animplantation method.
 7. The method as claimed in claim 1, wherein atleast one of: the layer containing the intermediate region is producedby an epitaxy method; or a base material for an embedding region, whichserves for embedding components of an integrated circuit arrangement, isproduced simultaneously during the epitaxy method.
 8. The method asclaimed in claim 7, wherein an epitaxy method for producing an epitaxiallayer is conducted in at least two stages, the epitaxial growth beinginterrupted, the interruption being followed by execution of at leastone other process, or the growth of the epitaxial layer being continuedafter the execution of the at least one other process.
 9. The method asclaimed in claim 1, wherein the terminal region leading to the regionnear the substrate laterally encompasses the intermediate region. 10.The method as claimed in claim 1, wherein the layer containing theintermediate region is a semiconductor layer which contains regions withdifferent conduction types.
 11. The method as claimed in claim 1,wherein the decoupling region adjoins material with a differentconduction type or is surrounded by material with a different conductiontype.
 12. An integrated circuit arrangement having a pin diodecomprising: a carrier substrate which carries a region sequence of a pindiode; a doped region of one conduction type, which is contained in theregion sequence and is near the substrate; a doped region remote fromthe substrate, which is contained in the region sequence, is furtheraway from the carrier substrate than the region near the substrate, andis of a different conduction type than the conduction type of the regionnear the substrate; an intermediate region which is arranged between theregion near the substrate and the region remote from the substrate andis undoped or provided with a weak doping in comparison with the dopingof the region near the substrate and the doping of the region remotefrom the substrate; an electrically conductive terminal region, whichleads to the region near the substrate and is arranged in a layercontaining the intermediate layer; a circuit arrangement carried by thecarrier substrate and containing at least two electronic components; adoped decoupling region arranged between one component and the carriersubstrate and of the same conduction type as the region near thesubstrate and arranged in one plane with the region near the substrate;and a circuit substrate, which is arranged between the decoupling regionand at least one of the components, the circuit substrate forming a pndiode or an np diode with the decoupling region, the decoupling regionbeing arranged between one portion of the components and the carriersubstrate and not between the other portion of the components and thecarrier substrate, and in a layer in which the region near the substrateand the decoupling region are arranged, regions outside the region nearthe substrate and the decoupling region are provided with a doping of adifferent conduction type or are undoped.
 13. The circuit arrangement asclaimed in claim 12, wherein the terminal region penetrates through thelayer from an interface remote from the substrate as far as an interfacenear the substrate.
 14. The circuit arrangement as claimed in claim 12,wherein the decoupling region has the same dopant concentration as theregion near the substrate.
 15. The circuit arrangement as claimed inclaim 14, further comprising an electrically conductive decouplingregion terminal region, at least one of: which leads to the decouplingregion; or which has the same material composition as the terminalregion leading to the region near the substrate.
 16. The method asclaimed in claim 6, wherein a depth of the trench is at least twice awidth of the trench.
 17. The method as claimed in claim 8, wherein theat least one other process comprises a doping process for fabricating adoping which differs from a doping of the epitaxial layer.
 18. Themethod as claimed in claim 9, wherein the terminal region leading to theregion near the substrate completely laterally encompasses theintermediate region.
 19. The method as claimed in claim 11, wherein thedecoupling region is surrounded by the material with a differentconduction type on all sides apart from one or a plurality of decouplingregion terminal regions.
 20. The method as claimed in claim 3, whereinthe decoupling region terminal region and the decoupling region form ashielding well which surrounds a region encompassed by the shieldingwell, relative to the side areas and the base area of the encompassedregion, by at least fifty percent or by at least seventy five percent.